NDLI: The Power of Priority: NoC Based Distributed Cache Coherency

Content Provider	IEEE Xplore Digital Library
Author	Bolotin, E. Guz, Z. Cidon, I. Ginosar, R. Kolodny, A.
Copyright Year	2007
Description	Author affiliation: Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa (Bolotin, E.; Guz, Z.; Cidon, I.; Ginosar, R.; Kolodny, A.)
Abstract	The paper introduces network-on-chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance chip multi processors (CMPs). We address previously proposed CMP architectures based on non uniform cache architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalities can provide infrastructure for the coherent access of both static and dynamic NUCA. Then we show how several low cost mechanisms incorporated into such a vanilla NoC can facilitate CMP and boost performance of a cache coherent NUCA CMP. The basic mechanism is based on priority support embedded in the NoC, which differentiates between short control signals and long data messages to achieve a major reduction in cache access delay. The low cost priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction. Priority-based NoC along with the discussed NoC interfaces are evaluated in detail using CMP-NoC simulations across several SPLASH-2 benchmarks and static Web content serving benchmarks showing substantial L2 cache access delay reduction and overall program speedup
Starting Page	117
Ending Page	126
File Size	233480
Page Count	10
File Format	PDF
ISBN	0769527736
DOI	10.1109/NOCS.2007.42
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Protocols Design methodology Network-on-a-chip Power system interconnection Traffic control Paper technology Network interfaces Delay Radio access networks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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