NDLI: Sensitivity based methodologies for process variation aware analog IC optimization

Content Provider	IEEE Xplore Digital Library
Author	Afacan, E. Berkol, G. Baskaya, F. Dundar, G.
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Electron. Eng., Bogazici Univ., Istanbul, Turkey (Afacan, E.; Berkol, G.; Baskaya, F.; Dundar, G.)
Abstract	With the continuous downscaling of CMOS technology over the last two decades, reliability of CMOS circuits has become a more critical design issue due to the worsening effects of process variations. Conventionally, variability analysis has been performed following the design process after which the design is modified based on the variation effects, if necessary. However, increased variation and mismatch problems have enforced designers to consider robustness as a design objective that should be maximized. Besides the variability problem, increased non-idealities with more advanced technologies have complicated circuit analysis, and caused unacceptably long design times. Therefore, design automation tools for analog circuits have become crucial to keep the synthesis time within acceptable limits even if variability analysis is included. In this paper, two different methodologies are proposed and discussed for variation aware design automation of analog circuits: Over-Design approach that is based on guard-banding the circuit performance and Variation-Aware Design approach depending on looking for more robust solutions in the dedicated search space. The superiorities of the proposed approaches are discussed via the synthesis results of a two stage OTA example.
Starting Page	1
Ending Page	4
File Size	255939
Page Count	4
File Format	PDF
ISBN	9781479949946
DOI	10.1109/PRIME.2014.6872737
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-06-30
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sensitivity Analog circuits Robustness Mathematical model Integrated circuit modeling Integrated circuit reliability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Analog behavior in custom IC variation-aware design

Robustness in analog systems: Design techniques, methodologies and tools

NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling

Yield-aware hierarchical optimization of large analog integrated circuits

Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits

A layout-aware automatic sizing approach for retargeting analog integrated circuits

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique

Advancements on reliability-aware analog circuit design

Sensitivity based methodologies for process variation aware analog IC optimization

Similar Documents

Analog behavior in custom IC variation-aware design

Robustness in analog systems: Design techniques, methodologies and tools

NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

Yield-aware analog integrated circuit optimization using geostatistics motivated performance modeling

Yield-aware hierarchical optimization of large analog integrated circuits

Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits

A layout-aware automatic sizing approach for retargeting analog integrated circuits

An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique

Advancements on reliability-aware analog circuit design

Sensitivity based methodologies for process variation aware analog IC optimization