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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Guoqiang Hang Xuanchang Zhou Yang Yang Danyan Zhang |
| Copyright Year | 2014 |
| Description | Author affiliation: Sch. of Inf. & Electr. Eng., Zhejiang Univ. City Coll., Hangzhou, China (Guoqiang Hang; Xuanchang Zhou; Yang Yang; Danyan Zhang) |
| Abstract | A No Race (NORA) dynamic logic using neuron-MOS transistor is presented. The circuit is designed using the n-channel neuron-MOS transistor instead of the nMOS logic block or pMOS logic block in the conventional NORA dynamic logic circuit. The proposed full-adder shows that the logic block of NORA circuit can be simplified by utilizing neuron-MOS transistor. A simple synthesis technique of the n-channel neuron-MOS logic block by employing summation signal is discussed. HSPICE simulation results using TSMC 0.35μm 2-ploy 4-metal CMOS process with 1.5V power supply, have verified the effectiveness of the proposed neuron-MOS-based NORA circuits. For comparison, the power consumption and the output delay of the proposed NORA adders are measured during the simulations. |
| Starting Page | 181 |
| Ending Page | 185 |
| File Size | 249942 |
| Page Count | 5 |
| File Format | |
| ISSN | 21579563 |
| e-ISBN | 9781479951512 |
| DOI | 10.1109/ICNC.2014.6975831 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-08-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Couplings Latches CMOS circuits neuron-MOS transistor NORA Switches Logic gates dynamic logic Transistors Adders MOS devices |
| Content Type | Text |
| Resource Type | Article |
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