NDLI: Yes, we can improve SoC yield

Content Provider	IEEE Xplore Digital Library
Author	Vial, J. Virazel, A.
Copyright Year	2009
Description	Author affiliation: Laboratoire ¿Informatique, de Robotique et de Microélectronique de Montpellier - LIRMM, Université de Montpellier II / CNRS, France (Vial, J.; Virazel, A.)
Abstract	With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. To address this problem during SoC development, memory cores are built with hardware redundancies. On the other hand, logic cores embedded in SoC usually do not have such redundancy capabilities. Therefore, manufacturing defects affecting these cores decrease the yield of the entire SoC. Consequently, meaningful techniques for SoC yield improvement must also consider logic cores. In this paper, we propose and investigate the usage of TMR architectures for logic cores to increase the overall SoC yield. In order to analyze the TMR effectiveness, we resort to two defects distribution models, the Poisson and negative binomial distributions, that are also compared. Results obtained on SoC examples demonstrate the interest of using TMR architectures for SoC yield enhancement purpose.
Starting Page	272
Ending Page	275
File Size	530089
Page Count	4
File Format	PDF
ISBN	9781424437337
DOI	10.1109/RME.2009.5201370
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-12
Publisher Place	Ireland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Manufacturing processes Redundancy Fault tolerant systems Hardware Silicon Circuit faults Logic arrays Robots Testing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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