NDLI: On the validation of embedded systems through functional ATPG

Content Provider	IEEE Xplore Digital Library
Author	Di Guglielmo, G.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci., Univ. of Verona, Verona (Di Guglielmo, G.)
Abstract	Increasing size and complexity of digital designs has made essential to address critical verification issues at the early stages of design cycle. Therefore, automated verification tools are necessary at higher levels of abstraction, but they are still in a prototyping phase. In this context, a valuable solution for the functional validation is represented by dynamic verification which exploits simulation-based techniques to stimulate the whole design under verification (DUV). To perform dynamic verification it is necessary to generate test sequences to be simulated on the DUV. This paper describes a functional test pattern generator which exploits two different paradigms: high-level decision diagrams (HLDDs) and extended finite state machines (EFSMs). HLDDs and EFSMs are deterministically explored by using propagation, justification, learning and backjumping. The integration of such strategies allows the ATPG to more efficiently analyze the state space of the design under verification and to generate very effective test sequences.
Starting Page	149
Ending Page	152
File Size	462127
Page Count	4
File Format	PDF
ISBN	9781424419838
DOI	10.1109/RME.2008.4595747
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-22
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Biological system modeling Computational modeling Automatic test pattern generation Logic gates Benchmark testing Registers Engines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Automatic generation of EFSMs and HLDDs for functional ATPG

An effective ATPG flow for Gate Delay Faults

Application of Test-View Modeling to Hierarchical ATPG

PBO-Based Test Compression

Write-through method for embedded memory with compression Scan-based testing

Analysis and comparison of functional verification and ATPG for testing design reliability

LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits

On benchmarking digital testing systems

PODEM-X: An Automatic Test Generation System for VLSI Logic Structures

On the validation of embedded systems through functional ATPG

Similar Documents

Automatic generation of EFSMs and HLDDs for functional ATPG

An effective ATPG flow for Gate Delay Faults

Application of Test-View Modeling to Hierarchical ATPG

PBO-Based Test Compression

Write-through method for embedded memory with compression Scan-based testing

Analysis and comparison of functional verification and ATPG for testing design reliability

LDS-ATPG: an automatic test pattern generation system for combinational VLSI circuits

On benchmarking digital testing systems

PODEM-X: An Automatic Test Generation System for VLSI Logic Structures

On the validation of embedded systems through functional ATPG