NDLI: UWB 3.1–10.6 GHz CMOS transmitter for system-on-a-chip nano-power pulse radars

Please wait, while we are loading the content...

2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

2011 7th Conference on Ph.D. Research in Microelectronics and Electronics

6th Conference on Ph.D. Research in Microelectronics & Electronics

2009 Ph.D. Research in Microelectronics and Electronics

2008 Ph.D. Research in Microelectronics and Electronics

2007 Ph.D Research in Microelectronics and Electronics Conference

Welcome message

Technical Progam Commitee

Table of contents

Efficient pipelined ADCs using integer gain MDACs

A non linear ADC for sensor linearization

Time-interleaved incremental data converters with low oversampling ratios

Calculation of sequence lengths in MASH 1-1-1 digital delta sigma modulators with a constant input

A fifth-order continuous-time sigma-delta modulator with 62-dB dynamic range and 2MHz bandwidth

Predicting noise and jitter in CMOS inverters

Substrate injection characterization in CMOS mixed signal systems on chip

A mesochronous physical link architecture for network-on-chip interconnects

Efficient design approach and advanced architectures for universal OFDM systems

A dynamically reconfigurable system-on-chip for implementing wireless MACs

1-V 13-GHz ultra low noise amplifier for system-on-a-chip radiometer in CMOS 90 nm

UWB 3.1–10.6 GHz CMOS LNA

The 1-V 24-GHz low-voltage low-power current- mode transmitter in 130-nm CMOS technology

A RF circuit design methodology dedicated to critical applications

High density integrated optoelectronic circuits for high speed photonic microsystems

A low-power 6.3 GHz FBAR overtone-based oscillator in 90 nm CMOS technology

PRIME 2007 High quality medium power RF-MEMS based impedance tuner for smart microsystem integration

Design of a current mode 6-bit 100 MS/s flash A/D converter with 0.75 pJ/conv-lev FoM

High-speed multi-bit continuous-time bandpass delta-sigma modulator

A cascaded CT ΣΔ modulator with NTF zero and simple mismatch tuning method using interstage feedback

An optimized two stages low power sinc3 filter for ΣΔ modulators

A fully-differential symmetrical OTA-based rail-to-rail switched buffer

Embedded security: New trends in personal recognition systems

Systems-on-chip: Use of test data compression technique for reducing test time

Optimizing the serialization factor in Networks-on-Chip: a case of study

HW/SW FPGA implementation of Vector Median Filter

A full custom front-end ASIC prototype “CMAD” for COMPASS-RICH-1 particle detector system

A current measurement system for automotive applications

A micro power capacitive sensor readout channel based on the chopper modulation technique

A low power CMOS interface circuit for three-axis integrated accelerometers

A software-defined radio based on sampled analog signal processing dedicated to digital modulations

An automatic pulse alignment method for slope controlled super-regenerative receiver systems

A low-power high dynamic-range sigma-delta modulator for a capacitive microphone sensor

Low-power and accurate operation of a CMOS smart temperature sensor based on bipolar devices and Σ̄ A/D converter

A CMOS integrated circuit for DNA hybridization detection with digital output and temperature control

VHDL-AMS modeling of an integrated gas flow sensor readout channel with pressure compensation.

A power-efficient LVDS driver circuit in 0.18-μm CMOS technology

Second harmonic 60-GHz power amplifiers in 130-nm CMOS

Low level and high linearity amplifiers in integrated technologies for satellite receivers: Technical issues of linearization techniques

A 0.13 μm CMOS stacked folded fully differential PA structure for W-CDMA Application

A Support Vector Machine based pedestrian recognition system on resource-limited hardware architectures

An ASIP approach for adaptive AVC Motion Estimation

Flexible hardware for fingerprint Image Processing

Noise reduction in fractional-N frequency synthesizers with multiphase VCO

Low voltage integrated astable multivibrator based on a single CCII

RTW VCO with switched-capacitor tuning for satellite communication applications

The factorial Delay Locked Loop: a solution to fulfill multistandard RF synthesizer requirements

UWB 3.1–10.6 GHz CMOS transmitter for system-on-a-chip nano-power pulse radars

Photodetector structures for standard CMOS imaging applications

Microbeam dynamic shaping by closed-loop electrostatic actuation using modal control

Tactile sensing arrays for humanoid robots

Experiencing with AMR sensor conditioning in automotive field

Scaling guidelines for CMOS linear analog design

Analog circuit design at and below VT + 2Vds,sat

Linear differential voltage-current converter

Analog circuit design based on independently driven double gate MOSfet

NIC-based capacitance multipliers for low-frequency integrated active filter applications

A linearity and power efficient design strategy for architecture optimization of gm-C biquadratic filters

A new noise-tolerant dynamic logic circuit design

Tri-state buffer/bus driver circuits in MOS current-mode logic

Design of completion detection circuits for self-timed systems operating in subthreshold regime

On the use of error correcting and detecting codes in secured circuits

Fault-tolerant logic gates using neuromorphic CMOS Circuits

Case study of fault-tolerant architectures for 90nm CMOS crythographic cores

Adaptive wavelet-based signal dejittering

A ground reflection theory of UWB transmission in the case of CEPT band limited spectrum

A decimation filter for a very large band signal in radioastronomy

Efficient acquisition and analysis of digital signals in pin-limited system-on-package.

Separating control and data processing in RT level virtual IP components

Statistical methodologies for integrated circuits design

Adaptive high performance ΣΔ modulator designs

Fostering the reuse and collaborative development of models in the AMS SoC design process

Technology scaling and low-power data converter design

State of the art and perspectives in RF and mm-wave microelectronics

Advanced silicon technologies for wireless communications

2006 Ph.D. Research in Microelectronics and Electronics

Research in Microelectronics and Electronics, 2005 PhD

UWB 3.1–10.6 GHz CMOS transmitter for system-on-a-chip nano-power pulse radars

Content Provider	IEEE Xplore Digital Library
Author	Zito, F. Zito, D. Pepe, D.
Copyright Year	2007
Description	Author affiliation: Univ. "Mediterranea" of Reggio Calabria, Reggio Calabria (Zito, F.)
Abstract	The building blocks of the transmitter for system-on-a-chip CMOS nano-power radar systems are presented. They consist of a novel fully integrated UWB pulse generator and a digitally programmable delay element. The pulse generator provides monocycle pulses with duration time close to 250 ps and 1-V peak-to-peak amplitude. In detail, the circuit provides a sinusoidal-like monocycle when activated by a negative edge of a trigger signal provided by a micro-controller. This activation can be delayed in the range 1-3 ns, by acting on a 5-bit programmable delay element, which provides a total set of 32 different delay times.
Starting Page	189
Ending Page	192
File Size	318221
Page Count	4
File Format	PDF
ISBN	9781424410002
DOI	10.1109/RME.2007.4401844
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-02
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pulse generation Delay effects Radio transmitters Circuits FCC CMOS technology Heart rate detection Radar applications System-on-a-chip Ultra wideband radar
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in