NDLI: Low-power high-speed current mode logic using Tunnel-FETs

Content Provider	IEEE Xplore Digital Library
Author	Wei-Yu Tsai Huichu Liu Xueqing Li Narayanan, V.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA (Wei-Yu Tsai; Huichu Liu; Xueqing Li; Narayanan, V.)
Abstract	Current mode logic (CML) circuits have been widely used in high-speed data transceivers. The lower-voltage-swing makes the switching speed of CML much higher than the static logic can achieve, so it is worthy to adopt the CML circuits at the cost of higher power consumption in the high-speed applications. In order to obtain a better power efficiency (Frequency/power) in CML, it is critical to reduce the power consumption while maintaining the high operating frequency. This paper proposes an alternative approach by building the CML circuits with tunneling-field-effect-transistor (Tunnel FETs or TFETs) to achieve a high-throughput, low-voltage interface circuit design. By taking advantage of its steep subthreshold slope (less than 60 mV/dec), TFET exhibits the same on/off current ratio at the input voltage swing interval much lower than that of the MOSFETs, which enables the supply voltage scaling in CML circuits. For a design target data-rate (20 Gbps for multiplexer and 50 Gbps for buffer), our simulations show that the proposed TFET CML circuits are able to reduce the supply voltage from 0.6 V in conventional Si FinFET CML circuits to as low as 0.3 V while using the same constant tail current. As a result, a power consumption reduction of approximately 50% is achieved by the proposed TFET CML circuits, making the TFET CML approach a promising candidate for future low-power, high-performance applications.
Starting Page	1
Ending Page	6
File Size	296131
Page Count	6
File Format	PDF
ISBN	9781479960163
ISSN	23248440
DOI	10.1109/VLSI-SoC.2014.7004179
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-06
Publisher Place	Mexico
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand low-power TFET Logic gates CML high-frequency FinFETs Silicon low-voltage Integrated circuit modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency

Tunnel Transistors for Low Power Logic

The layout implementations of high-speed low-power MCML cells

Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm

Low power and high speed current-mode memristor-based TLGs

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications

Development of a compact model for Tunnel FETs designed for circuit simulation

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Low-power high-speed current mode logic using Tunnel-FETs

Similar Documents

Tunnel FET based low voltage static vs dynamic logic families for energy efficiency

Tunnel Transistors for Low Power Logic

The layout implementations of high-speed low-power MCML cells

Efficient arithmetic logic gates using double-gate silicon nanowire FETs

Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm

Low power and high speed current-mode memristor-based TLGs

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications

Development of a compact model for Tunnel FETs designed for circuit simulation

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs

Low-power high-speed current mode logic using Tunnel-FETs