NDLI: Integration of TTA processor tools to Kactus2 IP-XACT design flow

Content Provider	IEEE Xplore Digital Library
Author	Matilainen, L. Lahti, S. Esko, O. Salminen, E. Hamalainen, T.D.
Copyright Year	2012
Description	Author affiliation: Tampere University of Technology, Department of Computer Systems, P.O. Box 553, 33101, Finland (Matilainen, L.; Lahti, S.; Esko, O.; Salminen, E.; Hamalainen, T.D.)
Abstract	This paper presents a new freely available, open source design flow to accelerate the usage of application-specific processors in System-on-Chip designs. The proposed flow combines our Transport-Triggered Architecture (TTA) processor toolset and Kactus2 IP-XACT design environment. The IP-XACT standard and our Kactus2 tool make it easy to integrate and configure intellectual property (IP) components from multiple vendors whereas the configurable TTA provides a fast and efficient path from C-to-VHDL. We present 3 use cases for TTA: as a ready-made fixed accelerator, a general-purpose processor, and a tailored application-specific processor. Moreover, management of instance-specific data in IP-XACT is discussed. The combined design flow is presented in detail step-by-step, and the user time spent on each step is evaluated. Provided that C source codes and IP-XACT library are available, a non-HW oriented engineer can implement an FPGA based multiprocessor product in less than 5 hours.
Starting Page	1
Ending Page	6
File Size	1131221
Page Count	6
File Format	PDF
ISBN	9781467322218
e-ISBN	9781467322232
e-ISBN	9781467322225
DOI	10.1109/NORCHP.2012.6403151
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-12
Publisher Place	Denmark
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	TTA SoC Generators IP-XACT System analysis and design Kactus2 C to VHDL TCE Libraries Hardware System-on-a-chip IP networks Field programmable gate arrays
Content Type	Text
Resource Type	Article

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