NDLI: A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip

Content Provider	IEEE Xplore Digital Library
Author	Latif, K. Rahmani, A. Seceleanu, T. Tenhunen, H.
Copyright Year	2011
Description	Author affiliation: ABB Corporate Research, Västerås, Sweden (Seceleanu, T.) \|\| University of Turku, Finland (Latif, K.; Rahmani, A.; Tenhunen, H.)
Abstract	A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.
Starting Page	1
Ending Page	4
File Size	1080816
Page Count	4
File Format	PDF
ISBN	9781457705144
e-ISBN	9781457705168
e-ISBN	9781457705151
DOI	10.1109/NORCHP.2011.6126734
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-14
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Detectors Switches Very large scale integration Reliability
Content Type	Text
Resource Type	Article

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