NDLI: A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 /spl mu/m CMOS

Content Provider	IEEE Xplore Digital Library
Author	Rantala, A. Martins, D.G. Aberg, M.
Copyright Year	2005
Description	Author affiliation: VTT Inf. Technol., Finland (Rantala, A.; Martins, D.G.; Aberg, M.)
Abstract	This paper presents a clock generator circuit for a high speed analog-to-digital converter (ADC). A time interleaved ADC requires an accurate clocking for the converter fingers. The target ADC has 12 interleaved fingers each running at speed of 166 MS/s which corresponds to equivalent sampling frequency of 2 GS/s. A delay-locked loop (DLL) based clock generator has been proposed to provide multiple clock signals for the converter. The DLL clock generator has been implemented with a 0.35 /spl mu/m SiGe BiCMOS process (only MOS-transistor were used in DLL) by Austria Micro Systems and it occupies 0.6 mm/sup 2/ silicon area. The measured jitter of the DLL is around 1 ps and the delay between phases can be adjusted at 1 ps accuracy.
Starting Page	114
Ending Page	117
File Size	169700
Page Count	4
File Format	PDF
ISBN	1424400643
DOI	10.1109/NORCHP.2005.1597002
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-21
Publisher Place	Finland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fingers Circuits Signal sampling Jitter Frequency Signal generators Delay Analog-digital conversion Clocks Silicon germanium
Content Type	Text
Resource Type	Article

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A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 /spl mu/m CMOS