NDLI: Modeling and mitigation techniques of the magnetic integrated structures parasitic capacitance

Content Provider	IEEE Xplore Digital Library
Author	Racasan, A.N. Pacurar, C. Munteanu, C. Topa, V. Micu, D.D. Hebedean, C.
Copyright Year	2012
Description	Author affiliation: Departament of Electrotechnics and Measurements Technical University of Cluj-Napoca Baritiu 26-28, RO-400027 Cluj-Napoca, Romania (Micu, D.D.; Hebedean, C.) \|\| Departament of Electrotechnics and Measurements, Technical University of Cluj-Napoca, Baritiu 26-28, RO-400027, Cluj-Napoca, Romania (Racasan, A.N.; Pacurar, C.; Munteanu, C.; Topa, V.)
Abstract	The magnetic planar technology is nowadays an attractive solution for designing the Electromagnetic Interference (EMI) filters due to its efficiency at high frequencies and its mechanical robustness. On the other hand, the general trend of reducing the dimensions of the integrated structures one inherently leads to the increase of their structural parasitic effects. Therefore, the minimization of the parasitic capacitances and inductances represents an important issue for increasing the performances of a magnetic integrated structure. In this light, the aim of this paper is to present the authors contribution to developed structural parasitic capacitance reduction solutions from devices realized in planar magnetic technology. Being structures with an important geometrical complexity, the structural parasitic capacitance cannot be defined by direct calculation expressions and it cannot be localized in one device, it being practically distributed in the space between the coil wirings that form the structure. So, in this paper, are proposed approached techniques to reduce the structural parasitic capacitance in planar magnetic integrated structures.
Starting Page	1
Ending Page	5
File Size	2208663
Page Count	5
File Format	PDF
ISBN	9781467328548
e-ISBN	9781467328562
e-ISBN	9781467328555
DOI	10.1109/UPEC.2012.6398555
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-09-04
Publisher Place	United Kingdom
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	planar magnetic integrated technology Insulation numerical modeling and mitigation Windings Electromagnetic interference Computation Magnetic resonance LC structure optimal staggered winding method structural parasitic capacitance Numerical models Parasitic capacitance
Content Type	Text
Resource Type	Article

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