NDLI: Array enhanced logical stochastic resonance in the presence of delta correlated noise

Content Provider	IEEE Xplore Digital Library
Author	Lei Zhang Yanchang Xiao Xiangping Wu
Copyright Year	2011
Description	Author affiliation: School of Information Science and Engineering, China Jiliang University, Hangzhou, China (Lei Zhang; Yanchang Xiao; Xiangping Wu)
Abstract	In the presence of noise floor, we investigate the logical stochastic resonance phenomenon in a parallel array consisting of bistable devices, which is driven by various cycling combinations of logic inputs. The probability of the correct logic output is calculated according to true table of logic relationships. In contrast with a single system, the significant logic response can be extracted in a wider optimal window of noise. Increasing the array size tends to expand the effective working parameter domain in which the reliable logic operation is able to occur. It is also demonstrated that the array enhanced logical stochastic resonance has a saturating effect at larger array size. The small or medium array size is good enough for one to obtain reliable logic operation. The present structure can be realized by a set of CMOS based circuits or nanoelectronic devices, and further work as the basic ingredient of general purpose hardware that has the potential for the reconfigurability.
Starting Page	2417
Ending Page	2421
File Size	801795
Page Count	5
File Format	PDF
ISBN	9781612841809
e-ISBN	9781612841816
DOI	10.1109/FSKD.2011.6019951
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-26
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Strontium Stochastic resonance Noise Logic gates Logic gate parallel array Arrays Reliability Noise measurement Floors Bistable system
Content Type	Text
Resource Type	Article

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