NDLI: BIST of interconnection lines in the pixel matrix of CMOS imagers

Content Provider	IEEE Xplore Digital Library
Author	Fei, R. Moreau, J. Mir, S.
Copyright Year	2013
Description	Author affiliation: TIMA Lab., UJF, Grenoble, France (Mir, S.) \|\| STMicroelectron., Grenoble, France (Fei, R.; Moreau, J.)
Abstract	Interconnection lines in the sensors of CMOS imagers are used for pixel bias, addressing and readout. Catastrophic faults in these lines can cause parts of the pixel matrix to operate incorrectly and produce image defects like residual stripes and bands in images. These kinds of image defects are often difficult to remove by the image processing correction algorithm, and they are clearly visible as a sort of noise pattern. Among the defects in the pixel array, these catastrophic faults have most important influence on yield. In addition, partially degraded metal lines cannot be detected on todays' standard industrial testers for image sensors. These defects can evolve into catastrophic faults and they are the main cause of customer returns for many products. This paper proposes two built-in self-test (BIST) solutions to catch these defects in the pixel array, taking into account the industrial test constraints, namely increase of fault coverage, decrease of test time and test cost minimization.
Sponsorship	IEEE Components, Packaging Manuf. Technol. Soc.
Starting Page	174
Ending Page	177
File Size	762611
Page Count	4
File Format	PDF
ISBN	9781479900398
e-ISBN	9781479900411
DOI	10.1109/IWASI.2013.6576068
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-13
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage measurement CMOS image sensors industrial test Delays System-on-chip Table lookup Circuit faults Photodiodes Electrical resistance measurement HFPN
Content Type	Text
Resource Type	Article

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