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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jean, J. Graillat, S. |
| Copyright Year | 2010 |
| Abstract | Recently, parallel computation has become necessary to take full advantage of the gains allowed by Moore’s law. Many scientific and engineering applications exhibit data parallelism but might not make full use of it. Some ubiquitous operations such that the dot product can easily be parallelized and then make good use of available hardware, like multi-core or GPU. In this paper, we provide two slightly different algorithms to perform dot product calculations in a finite field using floating-point arithmetic and implement them on the GPU architecture. To do so, we pack input integers into floating-point numbers and exploit the computational capabilities of GPU to their full extent to get the result efficiently. Using error-free transformations, we show that it is possible to reach speedups between 10 or 40 with the parallel versions, with an algorithm using nearly no modular reduction. |
| Starting Page | 80 |
| Ending Page | 87 |
| File Size | 647871 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424498161 |
| DOI | 10.1109/SYNASC.2010.10 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-09-23 |
| Publisher Place | Romania |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Performance evaluation Finite field Instruction sets Programming GPU GPGPU Graphics processing unit CUDA error-free transformations Computer architecture floating-point arithmetic FMA Kernel |
| Content Type | Text |
| Resource Type | Article |
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