NDLI: Design of a Hardware Architecture Based on Microcontrollers for the Implementation of Membrane Systems

Content Provider	IEEE Xplore Digital Library
Author	Gutierrez, A. Fernandez, L. Arroyo, F. Martinez, V.
Copyright Year	2006
Description	Author affiliation: Grupo de Computacion Natural, Univ. Politecnica de Madrid (Gutierrez, A.; Fernandez, L.; Arroyo, F.; Martinez, V.)
Abstract	The nature of the computation based on membranes, distributed, nondeterministic and massively parallel makes that the current hardware architectures, mainly based in the use of clusters of microprocessors, be not the most appropriate to house this type of systems; especially if we think about the associated costs to solutions that try to maximize the grade of potential parallelism. The use of microcontroller, in these cases, it could be considered like a viable alternative, by its low cost and its high processing capacity, of not being because its use is restricted to problems that can be adapted to the small amount of memory that this kind of devices has to store generic data. The present work describes in a exhaustive way the implementation of a low cost hardware prototype based on microcontrollers that making use of external memory modules is able to resolve the main problem of the small capacity of storage of these components. This way range of approachable problems is enlarged and its use becomes a real alternative to the solutions based on clusters of microprocessors. The adopted hardware architecture also endows from a great flexibility to the proposed solution, since, unlike others, it doesn't require modifications to adapt to anyone of the topologies of current membrane systems. It will be responsibility of the software component that we use, the implementation of the algorithms that reproduce the behavior of different membrane systems
Sponsorship	IEEE CPS
Starting Page	350
Ending Page	353
File Size	387960
Page Count	4
File Format	PDF
ISBN	076952740X
DOI	10.1109/SYNASC.2006.29
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-26
Publisher Place	Romania
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Costs Microcontrollers Microprocessors Prototypes Computer architecture Parallel processing Hardware Biomembranes Distributed computing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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