NDLI: Rethinking reverse converter design: From algorithms to hardware components

Content Provider	IEEE Xplore Digital Library
Author	Molahosseini, Amir Sabbagh Zarandi, Azadeh Alsadat Emrani Mirhosseini, Seyed Mostafa Hosseinzadeh, Mehdi
Copyright Year	2014
Description	Author affiliation: Department of Computer Engineering, Kerman Branch, Islamic Azad University Kerman, Iran (Molahosseini, Amir Sabbagh) \|\| Department of Computer Engineering, Science and Research Branch, Islamic Azad University Tehran, Iran (Zarandi, Azadeh Alsadat Emrani; Mirhosseini, Seyed Mostafa; Hosseinzadeh, Mehdi)
Abstract	The Residue Number System (RNS) has been recognized as a powerful tool to enhance distinct computing applications. Due to this, lots of researches have been done on RNS especially on its most challenging part, reverse converter, to achieve better circuit's parameters. Reverse converter's complexity makes researchers to mainly focus on suggesting new moduli sets or investigating new algorithms and arithmetic formulations to improve its performance. Although these suggested methods result in better reverse converters during the previous half century, new aspects should be considered for nowadays applications and constraints requirements. In this work, we want to rethink reverse converter design and show that efficiency can be achieved by other methods which are mainly not considered during its design. These methods are based on hardware aspects including dedicated modular addition components, hardware structure optimizations, efficient pipelining and clock gating. Each of them will be explained with their effects on reverse converter characteristics and behavior.
Starting Page	444
Ending Page	447
File Size	96737
Page Count	4
File Format	PDF
ISBN	9781479948338
DOI	10.1109/ISICIR.2014.7029561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-10
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Reverse Converter Design methodology Modulo Adders Computer architecture Hardware Delays Adders Residue Number System Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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