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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bao-Feng Li Yong Dou |
| Copyright Year | 2008 |
| Description | Author affiliation: Sch. of Comput., Nat. Univ. of Defense Technol., Changsha (Bao-Feng Li; Yong Dou) |
| Abstract | A novel subblock-based scheme for bit plane encoder (BPE) of EBCOT in JPEG2000 is presented to conquer the mismatch in access pattern to code block memory. A codeblock is partitioned into 4 times 4 subblocks and encoded subblock by subblock; each subblock is encoded as the traditional scheme. The new scheme is compatible to existing accelerating technologies, such as sample-parallel, pass-parallel, bit-plane-parallel. Moreover the parallelism between subblocks can be exploited. A subblock-parallel and sample-parallel BPE architecture is implemented in FPGA. The system throughput is improved from $O(N^{2})$ to O(N), and memory requirement for status is decreased by > 30%. Experimental results show that our design outperforms related works considered by at least 1.3X and up to 26X. |
| Starting Page | 814 |
| Ending Page | 817 |
| File Size | 292827 |
| Page Count | 4 |
| File Format | |
| ISBN | 9780769532783 |
| DOI | 10.1109/IIH-MSP.2008.171 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-08-15 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | EBCOT Subblock-based sheme JPEG2000 Bit-plane encoder Memory management Transform coding Computer architecture Throughput Encoding Image compression Registers Acceleration |
| Content Type | Text |
| Resource Type | Article |
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