NDLI: Leverage simulation for analyzing CBSE/MDD development process of embedded systems

Content Provider	IEEE Xplore Digital Library
Author	Pavetic, B. Land, R.
Copyright Year	2010
Description	Author affiliation: Infodom d.o.o, Zagreb, Croatia (Pavetic, B.) \|\| School of Innovation, Design, and Engineering, Mälardalen University, Västerås, Sweden (Land, R.)
Abstract	Distributed embedded systems usually have strict quality requirements which need to be verified, and the allocation of software to hardware needs to be considered throughout the whole development process. In this paper, we present usage of simulation in analyzing development process of embedded systems using CARMA principle which combines two paradigms - Component-Based Software Engineering and Model Driven Development. In development process two types of parallel modeling of hardware are distinguished: modeling of a virtual hardware structure and of the physical structure. Two kinds of verification activities are introduced: milestone verification, which integrates the product requirements into the process through frequent analyses and measurements of the development artifacts, and exploratory analysis, which is informal and carried out by individual developers, similar to debugging. Based on the process model, we have constructed a queuing network model, used for simulations to further explore the characteristics of the development model. Initial simulations give by hand that by increasing the amount of analysis and verification in a project, more errors are found with the same amount of effort and time. There are also dependencies on project risks and the strength of the analysis tool support.
Starting Page	375
Ending Page	379
File Size	496312
Page Count	5
File Format	PDF
ISBN	9781424486632
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-23
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	University of Split, FESB
Subject Keyword	Analytical models Embedded systems Computational modeling Hardware Software engineering Guidelines
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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