NDLI: A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Peiyuan Wan Wei Lang Rui Jin Chi Zhang Pingfen Lin
Copyright Year	2012
Description	Author affiliation: Beijing Embedded System Key Lab, Beijing University of Technology, Beijing, 100124, China (Peiyuan Wan; Wei Lang; Rui Jin; Chi Zhang; Pingfen Lin)
Abstract	A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-Vpp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 $mm^{2}$ in 0.13-μm CMOS.
Starting Page	80
Ending Page	82
File Size	576374
Page Count	3
File Format	PDF
ISBN	9781467323031
e-ISBN	9781467323055
DOI	10.1109/RFIT.2012.6401620
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-11-21
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power demand Flip-around digital-to-analog converter (FADAC) low-power Capacitors Prototypes CMOS technology opamp-sharing CMOS integrated circuits Calibration low-voltage pipelined analog-to-digital converter (ADC) Gain
Content Type	Text
Resource Type	Article

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A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS