NDLI: Automated formal verification of processors based on architectural models

Content Provider	IEEE Xplore Digital Library
Author	Kuhne, U. Beyer, S. Bormann, J. Barstow, J.
Copyright Year	2010
Description	Author affiliation: Abstract RT Solutions GmbH, Munich, Germany (Bormann, J.) \|\| LSV ENS de Cachan Cachan, France (Kuhne, U.) \|\| OneSpin Solutions GmbH Munich, Germany (Beyer, S.) \|\| Infineon Technologies Ltd, Bristol, UK (Barstow, J.)
Abstract	To keep up with the growing complexity of digital systems, high level models are used in the design process. In today's processor design, a comprehensive tool chain can be built automatically from architectural or transaction level models, but disregarding formal verification. We present an approach to automatically generate a complete property suite from an architecture description, that can be used to formally verify a register transfer level (RTL) implementation of a processor. The property suite is complete by construction, i.e. an exhaustive verification of all the functionality of the processor is ensured by the method. It allows for the efficient verification of single pipeline processors, including several advanced processor features like multicycle instructions. At the same time, the structured approach reduces the effort for verification significantly compared to a manual complete formal verification. The presented techniques have been implemented in the tool FISACo, which is demonstrated on an industrial processor.
Starting Page	129
Ending Page	136
File Size	471528
Page Count	8
File Format	PDF
ISBN	9781457707346
e-ISBN	9780983567806
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-20
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	FMCAD Inc
Subject Keyword	Program processors Pipelines Computer architecture Manuals Data models Registers Safety
Content Type	Text
Resource Type	Article

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