NDLI: Hardware prototyping of boolean function classification schemes for lossless data compression

Content Provider	IEEE Xplore Digital Library
Author	Reaz, M.B.I. Mohd-Yasin, F. Sulaiman, M.S. Tho, K. Yeow, K.H.
Copyright Year	2004
Description	Author affiliation: Fac. of Eng., Multimedia Univ., Selangor (Reaz, M.B.I.; Mohd-Yasin, F.; Sulaiman, M.S.; Tho, K.; Yeow, K.H.)
Abstract	In this paper, we present the realization of Boolean function classification schemes on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm is performed by incorporating Boolean function classification into Huffman coding. This allows for more efficient compression because the data has been categorized and simplified before the encoding is done. The design is followed by the timing analysts and circuit synthesis for the validation, functionality and performance of the designated circuit which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications. The average compression ratio is 25% to 37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz
Starting Page	47
Ending Page	51
File Size	634247
Page Count	5
File Format	PDF
ISBN	0780385888
DOI	10.1109/ICCCYB.2004.1437664
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-08-30
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Boolean functions Prototypes Data compression Hardware Encoding Timing Huffman coding Circuit analysis Field programmable gate arrays Compression algorithms
Content Type	Text
Resource Type	Article

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