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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yao Tao Gao Deyuan Fan Xiaoya Ren Xianglong |
| Copyright Year | 2012 |
| Abstract | Multi-operand adder is one of attractive solutions compared with a network of 2-operand adders for accelerating algorithms including a lot of addition operations. In this paper, an improved 3-operand floating-point (FP) adder has been presented. Firstly, the internal width of the adder has been given which is compatible with IEEE-Std754. Secondly, a realignment method processing sticky bits is used to make the architecture has the same accuracy with a FP adder which has a infinite internal width. Thirdly, a low cost method to detect catastrophic cancellation has been employed. Several sophisticated techniques, such as compound adder and Leading zero anticipation (LZA), are utilized to optimize the architecture. The implementation results show that the proposed architecture has a competitive area and delay by comparing with both a basic 3-operand FP adder and a network of 2-operand FP adders. A small data format version of the proposed architecture has been verified by an exhaustive testing. |
| Starting Page | 192 |
| Ending Page | 196 |
| File Size | 371708 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781467348737 |
| DOI | 10.1109/CIT.2012.58 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-10-27 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computers Accuracy 3-operand FP adder catastrophic cancellation Computer architecture process sticky bits Compounds Adders Delay Optimization |
| Content Type | Text |
| Resource Type | Article |
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