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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Huang, P.S. Chao, Y.C. Tsai, M.Y. Lin, P.C. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Mech. Eng., Chang Gung Univ., Taoyuan, Taiwan (Huang, P.S.; Chao, Y.C.; Tsai, M.Y.) || Assembly Eng. Dept., Nanya Technol. Corp., Taipei, Taiwan (Lin, P.C.) |
| Abstract | The pin-on-elastic-foundation (PoEF) test associated with theoretical equations is used for the strength determination of 3D-TSV thin memory die. FEM simulation is also applied to evaluate the test results and further provides an insight into failure mechanics. The 50μm-thick memory chips with Cu TSVs are tested, and the results of the applied load versus deflections and maximum loads for front-side and back-side surface controlling failures are obtained. It is found that the maximum loads at back-side controlled failure are slightly larger than those at front-side controlled failure either for on-via or away-from-via loading. And the maximum loads for on-via loading are lower than those for away-from-via loading by 16% for front-side failure and 26% for back-side failure. Based on the failure mechanism, the TSV structures in the memory chips are found to be one of dominant factors (or the weakest spots) of die strength. The detailed loading stresses and TSV-induced residual silicon stresses are calculated and then discussed in terms of controlling factors of chip strength. |
| Sponsorship | IEEE Compon., Pack., Manuf. Technol. Soc. |
| Starting Page | 202 |
| Ending Page | 206 |
| File Size | 1346522 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781479906673 |
| ISSN | 21505934 |
| DOI | 10.1109/IMPACT.2013.6706646 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-10-22 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Loading TSV Silicon Finite element analysis Die strength Thin die Through-silicon vias Stress Thermal stresses Load modeling |
| Content Type | Text |
| Resource Type | Article |
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