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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Mukai, M. Tomizawa, T. Takeda, D. Tandai, T. Wakutsu, T. Yamaga, A. Sakai, A. Kaburaki, S. Miyamoto, Y. Hosoyama, N. Tsurumi, H. |
| Copyright Year | 2004 |
| Description | Author affiliation: Corporate Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan (Mukai, M.; Tomizawa, T.; Takeda, D.; Tandai, T.; Wakutsu, T.; Yamaga, A.; Sakai, A.; Kaburaki, S.; Miyamoto, Y.) |
| Abstract | In this paper we discuss a software oriented modem LSI. At first, the target system is focused on 3GPP DS-FDD mode and signal processing complexity of the developed software simulator is measured. According to the signal processing requirement, modem functions are partitioned into hardware and software. At the same time, a layered modem architecture which is a kind of multiprocessor architecture is proposed. This architecture can perform parallel processing by plural CPU cores, and therefore, it can lower the CPU clock and make software simple. We consider the support service switching possibility for further discussion. Moreover we have developed an evaluation board system. Referring to the implementation results, we discuss hardware complexity and the amount of memory from the viewpoint of LSI development. |
| Starting Page | 2352 |
| Ending Page | 2356 |
| File Size | 1190166 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780379543 |
| ISSN | 10903038 |
| DOI | 10.1109/VETECF.2003.1285950 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-10-06 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Modems Computer architecture Signal processing Hardware Large scale integration Software performance Software measurement Clocks Parallel processing Multimedia systems |
| Content Type | Text |
| Resource Type | Article |
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