NDLI: Hierarchical design of a mu ITRON specification kernel: TR2

Content Provider	IEEE Xplore Digital Library
Author	Fukuoka, K. Yokozawa, A. Tamaru, K.
Copyright Year	1991
Description	Author affiliation: Dept. of Adv. Microprocessor Technol., Toshiba Corp., Kawasaki, Japan (Fukuoka, K.; Yokozawa, A.; Tamaru, K.)
Abstract	In designing the architecture of a realtime kernel, the problem of trading between functions and responses is always important. The authors describe the design approach of TR2 and show how they have solved the problem. TR2 is a realtime kernel for TX-series microprocessors based on the mu ITRON specification. TR2 employs a two-level hierarchical architecture. A basic kernel provides primitive constant-response functions, while an extension kernel provides various additional functions. TR2 executes these complex functions without locking dispatch. To provide useful programming elements, TR2 allows the complex functions to be requested in an interrupt handler. The complex functions are not executed immediately but deferred, and executed by a server task. With the architecture, TR2 assures constant responses for an interrupt handler and a task.
Starting Page	69
Ending Page	76
File Size	415530
Page Count	8
File Format	PDF
ISBN	0818624752
ISSN	10636749
DOI	10.1109/TRON.1991.213115
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-11-21
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Kernel Delay Protection Data structures
Content Type	Text
Resource Type	Article

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