NDLI: Input test data volume reduction based on test vector chains

Content Provider	IEEE Xplore Digital Library
Author	Pomeranz, I. Reddy, S.M.
Copyright Year	2010
Description	Author affiliation: School of Electrical & Computer Eng., Purdue University, W. Lafayette, IN 47907, U.S.A. (Pomeranz, I.) \|\| Electrical & Computer Eng. Dept., University of Iowa, Iowa City, IA 52242, U.S.A. (Reddy, S.M.)
Abstract	The concept of test vector chains was introduced in the context of simulation-based test generation. Test vector chains provide a specific algorithm for performing single-bit changes in order to obtain new test vectors from existing ones. In this algorithm, two test vectors t and t are used. The test vector chain C (t, t) is obtained by gradually modifying t into t. Starting from t, each additional test vector in C (t, t) is one bit further from t and one bit closer to t until t is obtained. It was demonstrated that a test set T has a significant number of test vector chains that are effective in (1) increasing the numbers of detections of faults that were targeted during the generation of T; (2) increasing the fault coverage of faults that were not targeted during the generation of T; and (3) increasing the fault coverage of target faults when T does not detect all the target faults.
Starting Page	240
Ending Page	240
File Size	157618
Page Count	1
File Format	PDF
ISBN	9781424458349
ISSN	15301877
e-ISBN	9781424458356
e-ISBN	9781424458332
DOI	10.1109/ETSYM.2010.5512753
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-24
Publisher Place	Czech Republic
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Circuit faults Fault detection Compaction Logic testing Test data compression Computational modeling Context modeling Performance evaluation Encoding
Content Type	Text
Resource Type	Article

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