NDLI: New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)

Content Provider	IEEE Xplore Digital Library
Author	Eklow, B. Bennetts, B.
Copyright Year	2006
Description	Author affiliation: Cisco Syst., Milpitas, CA (Eklow, B.; Bennetts, B.)
Abstract	There is an industry-wide initiative called IJTAG (I for Internal) that has been prompted by the fact that many device and board test engineers are using the IEEE 1149.1 test access port and its supporting hardware and instruction features to access a variety of device-internal instrumentation. The IJTAG initiative was started at ITC 2004 and is now supported by over 50 device design and test professionals from all sectors of the electronics industry. IJTAG was formed to control the proliferation of unusual uses and, in some cases, non-compliant design of the TAP, which culminated in the 2005 submission of a project authorisation request to the IEEE to standardise the new technology emerging from the study. The IJTAG initiative is now known as the IEEE PI687 draft standard for the access and control of instrumentation embedded within a semiconductor device. In the words of the PAR, this standard will develop a methodology for access to embedded test and debug features (but not the features themselves) via the IEEE 1149.1 test access port (TAP) and additional signals that may be required. The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features. This embedded tutorial describes the work carried out so far by the P1687 working group. The two presenters are members of the P1687 core group and they will reflect the very latest thinking of the group
Starting Page	253
Ending Page	254
File Size	89318
Page Count	2
File Format	PDF
ISBN	0769525660
DOI	10.1109/ETS.2006.33
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-05-21
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Instruments System testing Life testing Electronic equipment testing Logic testing Access protocols Hardware Electronics industry Authorization Semiconductor devices
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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