NDLI: Concurrent Test Implementations

Content Provider	IEEE Xplore Digital Library
Author	Molavi, S. McPheeters, T.
Copyright Year	2007
Description	Author affiliation: Broadcom Corp., Irvine (Molavi, S.)
Abstract	Today's large SOC devices include many different IP blocks which tested sequentially add significant test time to the production flow. Testing of several devices in parallel is one way to reduce test time and cost per device. However, as more functionality is added to the SOCs, the pin count will increase and limit the number of sites that can be tested in parallel. One method to reduce test time per device is to concurrently test multiple areas of the device at the one time. Concurrent test is a methodology to test various sections of the device in parallel. This paper will discuss three different types of concurrent test. The first type of concurrent test takes advantage of the ATE's per pin electronics to perform DC or frequency measure tests in parallel. One example is running several PLL clock tests at once. A second type of concurrent test makes use of the device's DFT modes to execute simultaneous tests on different IP blocks. An example of this is executing time consuming digital tests like scan concurrently with analog tests like RF tuners or serial ATA. A third method to reduce test time is to start a new test while the previous results are still being calculated. Processing captured data can be done at the same time other tests are being executed. This could be applied to the outputs of ADCs or DACs where large amounts of data are processed by one or more embedded processors in the ATE while subsequent tests are running. Some of these techniques require the implementation of DFT at design time to allow multiple blocks to function simultaneously and independently of each other. The test board must also be designed with careful consideration to concurrent test. The ATE will play a key role in that it must support concurrent test features in its hardware and software. Implementing concurrent test will result in higher throughput and lower test cost which every semiconductor company must obtain to stay competitive.
Starting Page	214
Ending Page	214
File Size	193780
Page Count	1
File Format	PDF
ISBN	9780769528908
ISSN	10817735
DOI	10.1109/ATS.2007.101
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronic equipment testing Sequential analysis Costs Semiconductor device testing Flow production systems Performance evaluation Frequency measurement Phase locked loops Clocks Radio frequency
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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