NDLI: Zero Cost Test Point Insertion Technique to Reduce Test Set Size and Test Generation Time for Structured ASICs

Content Provider	IEEE Xplore Digital Library
Author	Sethuram, R. Seongmoon Wang Chakradhar, S.T. Bushnell, M.L.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ (Sethuram, R.)
Abstract	Since structured application specific integrated chip (ASIC) products require very short turn around time, long automatic test pattern generation (ATPG) run time is undesirable. Large structured ASICs often require a large number of test patterns to achieve the desired fault coverage. This paper presents the first test point insertion technique for structured ASICs that can reduce test set sizes and ATPG run time. Only unused flip-flops in the structured ASIC design are used to implement test points, so the proposed technique does not incur any hardware overhead. Since test points are inserted during a post-layout step, considering both timing and layout information, hence test points can be inserted without changing the existing layout or routing. Novel gain functions are defined that specifically quantify the reduction in test volume and test time to select the best signal lines for inserting test points. The gain function described in this paper is also applicable to regular cell based ASICs. The proposed test point insertion technique can be used in conjunction with any compression technique (Jas et al., 2003) to further reduce the test volume. Experimental results clearly demonstrate the effectiveness and scalability of the proposed technique. Using less than 1% of extra flip-flops and very little run time for test point insertion, test generation time was reduced by up 42.9% and test data volume by up to 25.9% while also achieving a near 100% fault efficiency for very large industrial (400K-5M signal lines) designs
Starting Page	339
Ending Page	348
File Size	316537
Page Count	10
File Format	PDF
ISBN	0769526284
ISSN	10817735
DOI	10.1109/ATS.2006.260953
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-20
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Costs Automatic test pattern generation Application specific integrated circuits Flip-flops Hardware Timing Routing Scalability Signal generators
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in