NDLI: Dynamic test set generation for analog circuits and systems

Please wait, while we are loading the content...

2014 IEEE 23rd Asian Test Symposium

2013 22nd Asian Test Symposium

2012 IEEE 21st Asian Test Symposium

2011 Asian Test Symposium

2010 19th IEEE Asian Test Symposium

2009 Asian Test Symposium

2008 17th Asian Test Symposium

16th Asian Test Symposium (ATS 2007)

2006 15th Asian Test Symposium

14th Asian Test Symposium (ATS'05)

13th Asian Test Symposium

2003 Test Symposium

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

Proceedings 10th Asian Test Symposium

Proceedings of the Ninth Asian Test Symposium

Proceedings Eighth Asian Test Symposium (ATS'99)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259)

"The new frontier for testing: nanometer technologies"

BIST diagnostics. I. Simulation models

Configuring arithmetic pattern generators and response compactors from the RT-modules of a circuit

Test cycle count reduction in a parallel scan BIST environment

A BIST scheme for asynchronous logic

A methodology for minimum area cellular automata generation

A high-level synthesis method for weakly testable data paths

Alleviating DFT cost using testability driven HLS

Optimizing HW/SW codesign towards reliability for critical-application systems

An efficient procedure for obtaining implication relations and its application to redundancy identification

Economical importance of the maximum chip area

A probabilistic model for path delay faults

A new low-cost method for identifying untestable path delay faults

False-path removal using delay fault simulation

An automatic test pattern generator for at-speed robust path delay testing

Delay testing with double observations [high-speed ICs]

On a logical fault model H1SGLF for enhancing defect coverage

Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Fault characterization of low capacitance full-swing BiCMOS logic circuits

Rough-hierarchical testing for safety critical software

A structured testing approach for DSP software

I/sub DDQ/ test methodology and tradeoffs for scan/non-scan designs

Design for diagnosability of CMOS circuits

IDDQ defect detection in deep submicron CMOS ICs

ATE features for Iddq testing

A new technique to ensure quality of test patterns

Testing CPU based boards for functionality using bus cycle signature system

Non-intrusive testing of high-speed CML circuits

Fast window test method of hysteresis test

Development of a multi-channel PC-based hard disk drive Bode-plot generator

An optimal time expansion model based on combinational ATPG for RT level circuits

Static test compaction for scan-based designs to reduce test application time

A non-scan DFT method for controllers to achieve complete fault efficiency

Complete search in test generation for industrial circuits with improved bus-conflict detection

On testing of Josephson logic circuits consisting of RSFQ dual-rail logic gates

Testing for floating gates defects in CMOS circuits

Electron beam tester aided fault diagnosis for logic circuits based on sensitized paths

BIST TPG for combinational cluster (glue logic) interconnect testing at board level

Fault detection in a tristate system environment

Comprehensive interconnect BIST methodology for virtual socket interface

SRAM-based FPGA's: testing the interconnect/logic interface

Built-in self-test for multiple CLB faults of a LUT type FPGA

A diagnosis method for interconnects in SRAM based FPGAs

Testing and diagnosis of interconnect structures in FPGAs

An approach to the on-line testing of operational amplifiers

Self-dual duplication for error detection

On-line error detection schemes for a systolic finite-field inverter

Fault tolerance of a tree-connected multiprocessor system and its arraylike layout

Observation time reduction for IDDQ testing of bridging faults in sequential circuits

An off-chip current sensor for IDDQ testing of CMOS ICs

Integrated current sensing device for micro IDDQ test

A high speed I/sub DDQ/ sensor for low-voltage ICs

Power analysis of DRAMs

Consequences of port restrictions on testing address decoder faults in two-port memories

Dynamic power supply current testing of CMOS SRAMs

March PS(23N) test for DRAM pattern-sensitive faults

Dynamic test set generation for analog circuits and systems

DC nonlinear circuit fault simulation with large change sensitivity

BISTing switched-current circuits

Analog module metrology using MNABST-1 P1149.4 test chip

A methodology and design for effective testing of voltage-controlled oscillators (VCOs)

Theory and application of multiple attractor cellular automata for fault diagnosis

Formal design techniques-theory and engineering reality

Verification of asynchronous circuits with bounded inertial gate delays

Verification pattern generation for core-based design using port order fault model

Application of real-time temporal logic to design fault detection in responsive communication protocols

Design and simulation of a RISC-based 32-bit embedded on-board computer

A ring architecture strategy for BIST test pattern generation

Exploiting BIST approach for two-pattern testing

Evaluating BIST architectures for low power

A BIST structure to test delay faults in a scan environment

An examination of PRPG selection approaches for large, industrial designs

Test generation for synchronous sequential circuits to reduce storage requirements

Partitioning and reordering techniques for static test sequence compaction of sequential circuits

Vector restoration using accelerated validation and refinement

On speeding-up vector restoration based static compaction of test sequences for sequential circuits

Synthesis of sequential circuits with clock control to improve testability

A test pattern generation algorithm exploiting behavioral information

A diagnostic test generation procedure for combinational circuits based on test elimination

Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Test pattern generation for column compression multiplier

An efficient random-like testing

Microsystem Testing: Challenge Or Common Knowledge

Microsystems Testing: A Challenge

Bridging A Gap Between Microelectronics And Micromechanics Testing

Testing Embedded Memories: Is BIST The Ultimate Solution?

Testing Embedded Memories: Is Bist The Ultimate Solution? An Asic Designer's Point Of View

Testing Embedded Memories: Is Bist The Ultimate Solution? Testing Of Embedded Memories-the Aggregate

Testing Embedded Memories: Is BIST The Ultimate Solution? Answers to the Key Issues

A DFT methodology for high-speed MCM based on boundary scan techniques

Proceedings Sixth Asian Test Symposium (ATS'97)

Proceedings of the Fifth Asian Test Symposium (ATS'96)

Proceedings of the Fourth Asian Test Symposium

Proceedings of IEEE 3rd Asian Test Symposium (ATS)

Proceedings of 1993 IEEE 2nd Asian Test Symposium (ATS)

Proceedings First Asian Test Symposium (ATS `92)

Dynamic test set generation for analog circuits and systems

Content Provider	IEEE Xplore Digital Library
Author	Huynh, S. Seongwon Kim Soma, M. Jinyan Zhang
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA (Huynh, S.)
Abstract	In this paper, we present an approach to construct a set of dynamic test signals for analog circuits and systems. Testability transfer factors are introduced and we use them as the basis to construct an efficient test set. Fault detectability and fault coverage are defined. Two circuits from the suite of analog and mixed-signal circuits are used to evaluate our approach. The fault coverage is 100% for both circuits studied. The approach presented may be used to construct inputs signals for the selection of an external stimulus applied through an arbitrary waveform generator.
Starting Page	360
Ending Page	365
File Size	533926
Page Count	6
File Format	PDF
ISBN	0818682779
ISSN	10817735
DOI	10.1109/ATS.1998.741639
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-02
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing System testing Analog circuits Voltage MOSFETs Resistors Equations Impedance Intrusion detection H infinity control
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in