NDLI: Test and debug solutions for 3D-stacked integrated circuits

Content Provider	IEEE Xplore Digital Library
Author	Deutsch, S. Chakrabarty, K.
Copyright Year	2015
Description	Author affiliation: Duke Univ., Durham, NC, USA (Deutsch, S.; Chakrabarty, K.)
Abstract	Three-dimensional (3D) stacking using through-silicon vias (TSVs) promises higher integration levels in a single package, keeping pace with Moore's law. Testing has been identified as a showstopper for volume manufacturing of 3D-stacked integrated circuits (3D ICs). This work provides solutions to new challenges related to 3D test content, test access, diagnosis and debug. We analyze the the impact of thermo-mechanical stress due to TSV fabrication process on test quality. We propose a test-generation flow that takes TSV-induced stress into account by using stress-aware circuit models. Pre-bond TSV test is a challenge due to limited accessibility of TSV at the pre-bond stage. We develop a non-invasive method for TSV test and diagnosis using ring oscillators, duty-cycle detectors, and a regression model based on artificial neural networks. In order to efficiently deliver test content, 3D design-for-test (DfT) architectures are needed. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations and minimizes test time. Finally, post-silicon debug is a major challenge due to continuously increasing design complexity. We develop a low-cost debug architecture for massive signal tracing in 3D-stacked ICs with wide-I/O DRAM dies that significantly increases the observation window compared to traditional methods that use trace buffers.
Starting Page	1
Ending Page	10
File Size	1352212
Page Count	10
File Format	PDF
ISBN	9781467365789
DOI	10.1109/TEST.2015.7342421
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Through-silicon vias Three-dimensional displays Timing Integrated circuit modeling Automatic test pattern generation Libraries
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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