NDLI: Synthesis and optimization procedures for fully and easily testable sequential machines

Content Provider	IEEE Xplore Digital Library
Author	Devadas, S. Ma, H.-K.T. Newton, A.R. Sangiovanni-Vincentelli, A.
Copyright Year	1988
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA (Devadas, S.)
Abstract	A synthesis procedure is described that produces an optimized fully and easily testable logic implementation of a sequential machine from a state transition graph description of the machine. This logic-level implementation is guaranteed to be testable for all single stuck-at faults in the combinational logic. No access to the memory elements is required. The test sequences for these faults can be obtained using combinational test generation techniques alone. It is shown that an intimate relationship exists between state assignment and the testability of a sequential machine. A technique is also presented of don't-care minimization and added observability which ensures fully testable machines.
Starting Page	621
Ending Page	630
File Size	876295
Page Count	10
File Format	PDF
ISBN	0818608706
ISSN	10893539
DOI	10.1109/TEST.1988.207845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-09-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Sequential analysis Logic testing Circuit testing Circuit faults Logic circuits Constraint optimization Minimization Observability Costs Clocks
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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