NDLI: Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASIC

Content Provider	IEEE Xplore Digital Library
Author	Lurkins, J. Hill, D. Benware, B.
Copyright Year	2005
Description	Author affiliation: LSI Logic Corp. (Lurkins, J.; Hill, D.; Benware, B.)
Abstract	A case study implementing the reduced vector set feed forward minimum voltage (RVSFF MinVDD) defect screening method on a high volume 0.18mum ASIC is presented. RVSFF MinVDD outliers from a high speed transition delay fault (TDF) scan test were identified and exercised in high temperature operating life (HTOL), and then monitored on automatic test equipment (ATE) and functional circuit test (FCT) to help determine the impact on early failure rate (EFR) and shipped product quality level (SPQL). Defective parts per million (DPPM) improvements are evaluated under two conditions, 1) IDDQ outlier screening already exists at ATE and MinVDD outlier screening is added, and 2) MinVDD is the only outlier screen that has been implemented. The results indicate that an EFR improvement of approximately 100 DPPM is achieved with the implementation of the MinVDD outlier screen
Starting Page	7
Ending Page	1226
File Size	355860
Page Count	1220
File Format	PDF
ISBN	0780390385
DOI	10.1109/TEST.2005.1584090
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Feeds Voltage Application specific integrated circuits Circuit testing Automatic testing Life testing Delay Circuit faults Fault diagnosis Temperature
Content Type	Text
Resource Type	Article

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