NDLI: Applications of semiconductor test economics, and multisite testing to lower cost of test

Content Provider	IEEE Xplore Digital Library
Author	Evans, A.C.
Copyright Year	1999
Description	Author affiliation: Teradyne Inc., Allentown, PA, USA (Evans, A.C.)
Abstract	This paper develops a Semiconductor Test Economic Model that can easily be applied to lowering overall cost of test and improving throughput. The "Model", designed to take the complexity out of Test Economics, describes all the variables that make up cost per unit, and using managerial economic concepts, illustrates how they interact with each other, as well as the overall production goal of minimizing costs while maximizing throughput. This paper is written for Test Managers, Test Engineers, Product Engineers, and ATE Capital Equipment Buyers for the purpose of gaining insight analyzing test economics, in order to make better decisions on everyday Manufacturing issues related to: test time reduction, multisite testing, yield, handler index time, ATE utilization, and ATE purchasing.
Starting Page	113
Ending Page	123
File Size	1468129
Page Count	11
File Format	PDF
ISBN	0780357531
ISSN	10893539
DOI	10.1109/TEST.1999.805620
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Semiconductor device testing Economic indicators Throughput Cost benefit analysis Engineering management Design engineering Production Pulp manufacturing Investments Semiconductor device manufacture
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

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