NDLI: A hybrid fault simulator for synchronous sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Krieger, R. Becker, B. Keim, M.
Copyright Year	1994
Description	Author affiliation: J.W. Goethe Univ., Frankfurt, Germany (Krieger, R.; Becker, B.; Keim, M.)
Abstract	Fault simulation for synchronous sequential circuits is a very time-consuming task. The complexity of the task increases if there is no information available about the initial state of the circuit. In this case, an unknown initial state is assumed which is usually handled by introducing a three-valued logic. It is known that fault simulation based upon this logic only determines a lower bound for the fault coverage achieved by a test sequence. Therefore, we developed a hybrid fault simulator H-FS combining the advantages of a fault simulator using the three-valued logic and of an exact symbolic fault simulator based upon binary decision diagrams. H-FS is able to handle even the largest benchmark circuits and thereby determines fault coverages much more accurately than previous algorithms using the three-valued logic.
Starting Page	614
Ending Page	623
File Size	1022719
Page Count	10
File Format	PDF
ISBN	0780321030
ISSN	10893539
DOI	10.1109/TEST.1994.528006
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-02
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Circuit simulation Sequential circuits Circuit testing Logic testing Computational modeling Data structures Boolean functions Computer science Benchmark testing
Content Type	Text
Resource Type	Article
Subject	Applied Mathematics Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Advanced fault collapsing (logic circuits testing)

Diagnostic Fault Simulation of Sequential Circuits

HTDD based parallel fault simulator

MULTIPLE-FAULT SIMULATION AND COVERAGE OF DETERMINISTIC SINGLE-FAULT TEST SETS

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy

FAST-SC: Fast Fault Simulation in Synchronous Sequential circuits

On potential fault detection in sequential circuits

A concurrent fault simulation for crosstalk faults in sequential circuits

Parallel sequence fault simulation for synchronous sequential circuits

A hybrid fault simulator for synchronous sequential circuits

Similar Documents

Advanced fault collapsing (logic circuits testing)

Diagnostic Fault Simulation of Sequential Circuits

HTDD based parallel fault simulator

MULTIPLE-FAULT SIMULATION AND COVERAGE OF DETERMINISTIC SINGLE-FAULT TEST SETS

Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy

FAST-SC: Fast Fault Simulation in Synchronous Sequential circuits

On potential fault detection in sequential circuits

A concurrent fault simulation for crosstalk faults in sequential circuits

Parallel sequence fault simulation for synchronous sequential circuits

A hybrid fault simulator for synchronous sequential circuits