NDLI: A new storage scheme for conflict-free vector access

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A new storage scheme for conflict-free vector access

Content Provider	IEEE Xplore Digital Library
Author	Kin-Man Lam Wan-Chi Siu Jun-Xun Yin Kai-Ming Tse
Copyright Year	1993
Description	Author affiliation: Dept. of Electron. Eng., Hong Kong Polytech., Kowloon, Hong Kong (Kin-Man Lam; Wan-Chi Siu; Jun-Xun Yin; Kai-Ming Tse)
Abstract	Investigations into data storage schemes for parallel memory system of vector processing have been mainly focused on low-order interleaved schemes, skewed schemes and XOR schemes. In this paper, a new interleaved storage scheme, namely k-row interleaved scheme, is suggested and investigated. This scheme allocates k consecutive data of a vector onto one memory module sequentially and then the next k consecutive data onto the next memory module. The address mapping functions are devised and the performance of this scheme is evaluated. It is found that this scheme improves the average performance for vector access over the previous schemes. The address generation hardware is also shown to be simple.
Starting Page	32
Ending Page	35
File Size	256957
Page Count	4
File Format	PDF
ISBN	0780312333
DOI	10.1109/TENCON.1993.319921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-10-19
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data engineering Memory Hardware Concurrent computing Degradation Length measurement Time measurement
Content Type	Text
Resource Type	Article

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