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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Konwat, John Clifford Yap, Roderick |
| Copyright Year | 2014 |
| Description | Author affiliation: Department of Electronics Engineering, De La Salle University Manila, Philippines (Konwat, John Clifford; Yap, Roderick) |
| Abstract | When designing an integrated circuit, simulation should normally pass through 5 corner libraries. The ideal case is to have the simulation results showing the same performance for all the corner libraries. However, owing to the difference in specifications among libraries, there can be significant variations of one result over another per library. In this paper, a fully integrated CMOS RC Clock circuit topology design is presented. The circuit was designed to have minimal sensitivity to process corner library variations. The design can operate at a low voltage of 1.5V using the 0.25um library. Simulation shows the clock output frequency remains stable at 50 kHz for all process corner libraries with a maximum deviation of only 6%. An added feature of the circuit is the variation of the clock's duty cycle. The entire design is fitted in an area of 1.11um2. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 284866 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781479940769 |
| ISSN | 21593450 |
| e-ISBN | 9781479940752 |
| DOI | 10.1109/TENCON.2014.7022282 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-10-22 |
| Publisher Place | Thailand |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Clocks Generators Low voltage Libraries Photonic band gap CMOS integrated circuits Sensitivity RC clock generator low sensitivity low frequency |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Computer Science Applications |
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