NDLI: Impact of architecture choices on DSP circuits

Content Provider	IEEE Xplore Digital Library
Author	Parhi, KK.
Copyright Year	1992
Description	Author affiliation: Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA (Parhi, KK.)
Abstract	Selection of proper architecture and implementation styles can strongly influence the performance of dedicated VLSI DSP circuits. The impact of architecture choices is illustrated by considering a number of representative signal processing examples and a few general architecture transformation techniques. It is shown that algorithm transformation techniques such as look-ahead computation can create concurrency in nonconcurrent recursive signal processing algorithms, and that inherently new signal processing algorithms are processed with concurrency. This leads to pipelined algorithm topologies without any hardware overhead. To illustrate the impact of the implementation styles, it is shown that the internal redundant number system can lead to more efficient realization of multipliers and adders. Using systematic folding and unfolding techniques, digit-serial architectures with no restrictions on the digit size can be described. All of these architectural techniques can increase the performance of DSP circuits.
Starting Page	784
Ending Page	788
File Size	384887
Page Count	5
File Format	PDF
ISBN	0780308492
DOI	10.1109/TENCON.1992.271863
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-11-11
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Digital signal processing Circuits Signal processing algorithms Signal design Algorithm design and analysis Pipeline processing Signal processing Hardware Delay Very large scale integration
Content Type	Text
Resource Type	Article

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