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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Meher, P. Mahapatra, K.K. |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electronics and communication, National Institute of Technology, Rourkela, India-769008. (Meher, P.; Mahapatra, K.K.) |
| Abstract | Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting. |
| Starting Page | 1175 |
| Ending Page | 1179 |
| File Size | 988113 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781457702563 |
| ISSN | 21593450 |
| e-ISBN | 9781457702556 |
| DOI | 10.1109/TENCON.2011.6129297 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-11-21 |
| Publisher Place | Indonesia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic gates Noise Transistors Clocks Delay Partial discharges MOS devices semi-dynamic logic Dynamic logic domino logic diode-footed domino noise tolerance power consumption robustness technology scaling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Computer Science Applications |
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