Please wait, while we are loading the content...
| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Paramasivam, K. Gunavathi, K. Nirmalkumar, A. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of EEE, Bannari Amman Inst. of Technol., Sathyamangalam (Nirmalkumar, A.) || Dept. of ECE, PSG Coll. of Technol., Coimbatore (Gunavathi, K.) || PSG Coll. of Technol., Coimbatore (Paramasivam, K.) |
| Abstract | Latest VLSI circuits face the problem of power dissipation not only in design phase but also during testing phase. Power dissipation during testing may be increased up to three times more than that during normal operation. Testing power, testing time and test area overhead are the critical parameters to be optimized for large and complex VLSI circuits. Scan architectures are widely used in testing of sequential circuits. In this paper, modified scan architecture is proposed to reduce shift and capture power, testing time and test area overhead in scan testing. The scan architecture is modified such that the number of transitions during shift and capture process is reduced. Modification is carried out by eliminating an inverter in the serial path of scan latch. Hence the scan cell not only reduces the power but also reduces the test area overhead and critical path delay in scan chain. The reduction in critical path delay of scan cell improves the speed during testing process and normal operation of circuit. The experimental results with benchmark circuits (ISCAS 89) show that a favorable reduction is achieved in the shifting and capture power, test area overhead and critical path delay. |
| Sponsorship | IEEE Region 10 |
| Starting Page | 1 |
| Ending Page | 6 |
| File Size | 208407 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781424424085 |
| DOI | 10.1109/TENCON.2008.4766794 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-11-19 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Circuit testing Logic testing Delay Very large scale integration Integrated circuit testing Built-in self-test Power dissipation Automatic testing Educational institutions Clocks test area overhead scan testing scan cell test power |
| Content Type | Text |
| Resource Type | Article |
National Digital Library of India (NDLI) is a virtual repository of learning resources which is not just a repository with search/browse facilities but provides a host of services for the learner community. It is sponsored and mentored by Ministry of Education, Government of India, through its National Mission on Education through Information and Communication Technology (NMEICT). Filtered and federated searching is employed to facilitate focused searching so that learners can find the right resource with least effort and in minimum time. NDLI provides user group-specific services such as Examination Preparatory for School and College students and job aspirants. Services for Researchers and general learners are also provided. NDLI is designed to hold content of any language and provides interface support for 10 most widely used Indian languages. It is built to provide support for all academic levels including researchers and life-long learners, all disciplines, all popular forms of access devices and differently-abled learners. It is designed to enable people to learn and prepare from best practices from all over the world and to facilitate researchers to perform inter-linked exploration from multiple sources. It is developed, operated and maintained from Indian Institute of Technology Kharagpur.
Learn more about this project from here.
NDLI is a conglomeration of freely available or institutionally contributed or donated or publisher managed contents. Almost all these contents are hosted and accessed from respective sources. The responsibility for authenticity, relevance, completeness, accuracy, reliability and suitability of these contents rests with the respective organization and NDLI has no responsibility or liability for these. Every effort is made to keep the NDLI portal up and running smoothly unless there are some unavoidable technical issues.
Ministry of Education, through its National Mission on Education through Information and Communication Technology (NMEICT), has sponsored and funded the National Digital Library of India (NDLI) project.
| Sl. | Authority | Responsibilities | Communication Details |
|---|---|---|---|
| 1 | Ministry of Education (GoI), Department of Higher Education |
Sanctioning Authority | https://www.education.gov.in/ict-initiatives |
| 2 | Indian Institute of Technology Kharagpur | Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project | https://www.iitkgp.ac.in |
| 3 | National Digital Library of India Office, Indian Institute of Technology Kharagpur | The administrative and infrastructural headquarters of the project | Dr. B. Sutradhar bsutra@ndl.gov.in |
| 4 | Project PI / Joint PI | Principal Investigator and Joint Principal Investigators of the project |
Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon |
| 5 | Website/Portal (Helpdesk) | Queries regarding NDLI and its services | support@ndl.gov.in |
| 6 | Contents and Copyright Issues | Queries related to content curation and copyright issues | content@ndl.gov.in |
| 7 | National Digital Library of India Club (NDLI Club) | Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach | clubsupport@ndl.gov.in |
| 8 | Digital Preservation Centre (DPC) | Assistance with digitizing and archiving copyright-free printed books | dpc@ndl.gov.in |
| 9 | IDR Setup or Support | Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops | idr@ndl.gov.in |
|
Loading...
|