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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chandwani, M. Dandekar, P.W. Sharma, P.C. |
| Copyright Year | 1989 |
| Description | Author affiliation: Dept. of Comput. & Electron. Eng., Shri G.S. Inst. of Technol. & Sci., Indore, India (Chandwani, M.; Dandekar, P.W.; Sharma, P.C.) |
| Abstract | The design aspects of the topology of the architecture based on specifications are discussed. The simulation modeling of the proposed architecture is described. It is based on uniformly distributed random numbers representing the probability of a request from a processor for local memory or a shared memory at a higher level bus in the multilevel architecture. The results of the simulation are presented, and the performance of a single time-shared bus structure is compared with a multilevel hierarchical bus structure. The multi level hierarchical structure is found to offer better performance. |
| Starting Page | 197 |
| Ending Page | 200 |
| File Size | 351061 |
| Page Count | 4 |
| File Format | |
| DOI | 10.1109/TENCON.1989.176923 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-11-22 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Memory architecture Throughput Computer architecture Circuit topology Computational modeling Visualization Aggregates Couplers |
| Content Type | Text |
| Resource Type | Article |
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