NDLI: Development of timing driven IP design flow based on physical knowledge synthesis

Content Provider	IEEE Xplore Digital Library
Author	Kumaraswamy, A.K. Erdogan, A.T. Atluri, I.
Copyright Year	2004
Description	Author affiliation: Sch. of Eng. & Electron., Edinburgh Univ., UK (Kumaraswamy, A.K.; Erdogan, A.T.; Atluri, I.)
Abstract	Over the last three years, many of the big vendors in electronic design automation have focused their R&D efforts on all-in-one RTL-to-GDSII tool suites that tie together logical or register-transfer-level design and synthesis with floor planning, placement and routing. The idea is that linking these tools tightly in a single flow better equip engineers to deal with the timing, power and signal-integrity issues of deep-submicron fabrication processes by letting them write RTL and perform synthesis, placement and routing in a single pass. The result is to get designs out of the door more quickly. Recent CAD methodologies such as SP&R from Cadence have made an attempt to address issues of timing closures and design reliability both of which are gaining significance as device geometries continues to shrink further into the deep submicron realm. Addressing these issues requires new levels of integration between logic design and physical implementation technologies. This paper proposes a timing driven IP design flow based on PKS technology. The study progressed with the development of script files for efficient timing. The preliminary results indicate 5% efficiency in the timing.
Sponsorship	IEEE Circuits and Syst. Soc. Micronet R&D iCore Univ. of Calgary, Canada Alberta Innovations and Sci
Starting Page	193
Ending Page	197
File Size	250271
Page Count	5
File Format	PDF
ISBN	0769521827
DOI	10.1109/IWSOC.2004.1319877
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-19
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Signal synthesis Routing Electronic design automation and methodology Research and development Joining processes Power engineering and energy Signal processing Fabrication Design automation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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