NDLI: Analog implementation of BRIN for optimization problems

Content Provider	IEEE Xplore Digital Library
Author	Ng, H.S. Lam, K.P.
Copyright Year	2002
Description	Author affiliation: Dept. of Syst. Eng. & Eng. Manage., Chinese Univ. of Hong Kong, Shatin, China (Ng, H.S.; Lam, K.P.)
Abstract	The binary relation inference network (BRIN) shows promise in obtaining the global optimal solution in a time independent of the problem size. However, the realization of this merge is dependent on the implementation platforms. In this paper, analog implementation of BRIN for two different directed graph problems is studied. As transitive closure problems can transform to a special case of shortest path problems or a special case of maximum spanning tree problems, two different forms of BRIN are discussed. Their circuits using common nalog integrated circuits are investigated. Also, the BRIN solution for critical path problems is expreassed. It is implemented using the separated building block circuit and the combined building block circuit. As these circuits are different, the response time of the network will be different. However, a simple circuit does not promise to give a faster solution time for BRIN.
Sponsorship	IEEE Region 10 IEEE Comput. Soc. Beijing Chapter IEEE Commun. Soc. Beijing Chapter IEEE Control Syst. Soc. Beijing Chapter IEEE Power Eng. Soc. Beijing Chapter IEEE Power Electron. Soc. Beijing Chapter IEEE Signal Process. Soc. Biejing Chapter
Starting Page	637
Ending Page	640
File Size	394405
Page Count	4
File Format	PDF
ISBN	0780374908
DOI	10.1109/TENCON.2002.1181355
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-10-28
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Costs Shortest path problem Parallel processing Clustering algorithms Search methods Tree graphs Analog integrated circuits Delay Analog circuits Dynamic programming
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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