NDLI: Design and implementation of FPGA based wavepipelined fast convolver

Content Provider	IEEE Xplore Digital Library
Author	Lakshminarayanan, G. Venkataramani, B. Senthilkumar, K.P. Kottapalli, M.S.V.A.
Copyright Year	2000
Description	Author affiliation: Regional Eng. Coll., Tiruchirappalli, India (Lakshminarayanan, G.)
Abstract	A new parallel/serial convolver scheme with wavepipelining is proposed first. The design of the wavepipelined (WP) convolver using FPGAs is considered next. Convolvers with and without wavepipelining are implemented using Xilinx XC4006E FPGAs for convolving two sequences each with 8 bit accuracy and sequence length 8. The convolver without wavepipelining requires 125 CLBs and permits a minimum sampling period of 176 nsec. The WP convolver requires 217 CLBs and permits a minimum sampling period of 92 nsec. Further the multipliers in the WP convolver do not require the latches and an ASIC for a large WP convolver can result in significant savings in area and power. Finally three schemes for increasing the sampling rate of the WP convolver are suggested.
Starting Page	212
Ending Page	217
File Size	447101
Page Count	6
File Format	PDF
ISBN	0780363558
DOI	10.1109/TENCON.2000.892259
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-24
Publisher Place	Malaysia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Convolvers Sampling methods Pipeline processing Digital signal processing Throughput Convolution Educational institutions Postal services Latches
Content Type	Text
Resource Type	Article

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