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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dramicanin, D.M. Pejovic, V. Petrovic, Z. |
| Copyright Year | 2007 |
| Description | Author affiliation: Bitgear Wireless Design Services d.o.o, Belgrade (Dramicanin, D.M.) |
| Abstract | A field programmable gate array (FPGA) chip is characterised by intrinsic functional changeability. This motive has turned them into a widely accepted tool for rapid prototyping and test of hardware systems and/or subsystems. On the other hand, their role as a final product delivery platform is insignificant, mostly due to price constrains. The concept of interactive reconfigurable firewall, which is studied here, will serve as an example of a design ideal to be deployed in an FPGA even in the final market targeted instance. The paper introduces and studies the mentioned concept together with the design challenges derived form the specific nature of the application. In the same time the exploitation scenario of the concept is, deeply embedded within the concept itself, justifies the decision to target an FPGA chip for final commercialisation of the concept by relativising the inferred cost effects of one such decision. The last statement is documented by the user-capacity estimation also presented here. |
| Starting Page | 597 |
| Ending Page | 600 |
| File Size | 360215 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424414673 |
| DOI | 10.1109/TELSKS.2007.4376085 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-09-26 |
| Publisher Place | Serbia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Field programmable gate arrays Hardware Costs Telecommunication traffic Performance analysis Engines Prototypes System testing State estimation Security FPGA Firewall reconfiguration |
| Content Type | Text |
| Resource Type | Article |
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