NDLI: Fault tolerant Block Based Neural Networks

Content Provider	IEEE Xplore Digital Library
Author	Haridass, S.s.K. Hoe, D.
Copyright Year	2010
Description	Author affiliation: Electrical Engineering Department, University of Texas at Tyler, Tyler, TX 75799 USA (Haridass, S.s.K.; Hoe, D.)
Abstract	Block Based Neural Networks (BBNNs) have shown to be a practical means for implementing evolvable hardware on reconfigurable fabrics for solving a variety of problems that take advantage of the massive parallelism offered by a neural network approach. This paper proposes a method for obtaining a fault tolerant implementation of BBNNs by using a biologically inspired layered design. At the lowest level, each block has its own online detection and correcting logic combined with sufficient spare components to ensure recovery from permanent and transient errors. Another layer of hierarchy combines the blocks into clusters, where a redundant column of blocks can be used to replace blocks that cannot be repaired at the lowest level. The hierarchical approach is well-suited to a divide-and-conquer approach to genetic programming whereby complex problems are subdivided into smaller parts. The overall approach can be implemented on a reconfigurable fabric.
Starting Page	357
Ending Page	361
File Size	551362
Page Count	5
File Format	PDF
ISBN	9781424456901
ISSN	00942898
e-ISBN	9781424456918
DOI	10.1109/SSST.2010.5442804
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault tolerance Neural networks Fabrics Integrated circuit interconnections Circuit faults Fault tolerant systems Neural network hardware Fault detection Network topology Logic Fault detection and correction Reconfigurable logic Block based network
Content Type	Text
Resource Type	Article

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