NDLI: The effect of the power line impedance to the stabipity of the system adopting the intermediate bus power supppy architecture

Content Provider	IEEE Xplore Digital Library
Author	Hisanaga, K. Nagao, M. Harada, K.
Copyright Year	2007
Description	Author affiliation: NEC Infrontia Corp., Tokyo (Hisanaga, K.)
Abstract	During the course of the past few years, operating voltages of silicon devices have been reduced and as a result, additional power supply operating voltages are required for system operation. In order to meet these reduced voltages, the intermediate bus power supply architecture has been widely adopted for large scale communication systems. This architecture comprises of a let stage dc-dc converter (Intermediate Bus Converter) and 2nd stage dc-dc converters (Point of Load:POL) [1] [2]. The analysis of the effect of power line impedance located outside the system for the stability of the conventional architecture have already been introduced [3]. In addition, many efforts have also been made in order to analyze the stability inside the system adopting the intermediate bus architecture[6]~[12]. However, the analysis of the effect of power line impedance located outside the system to the stability of the communication system adopting the intermediate bus power supply architecture has not been initiated. Therefore, this paper provides detailed analysis of the effect of power line impedance located outside the system to the stability of the system adopting the intermediate bus power supply architecture. This paper will analyze and derive the end result necessary for stable operability of communication systems as follows: We will conclude that, 1) The use of the intermediate bus power supply architecture for operation with power line impedance ie more stable as opposed to the conventional power supply architecture 2) In general, by the use of even numbered regulated conversion stage power supply architecture, ie more stable against the power line impedance than by the use of odd number conversion stage power supply architecture. Finally, the validity of these results ie verified by comparison between the analytical result and the simulation result.
Starting Page	327
Ending Page	332
File Size	334424
Page Count	6
File Format	PDF
ISBN	9781424416271
DOI	10.1109/INTLEC.2007.4448792
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-30
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Impedance DC-DC power converters Voltage Cutoff frequency Transfer functions National electric code Laboratories Tellurium Power systems Resonant frequency
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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