NDLI: Pattern design criteria of main circuit using printed circuit boards for parasitic inductance reduction

Content Provider	IEEE Xplore Digital Library
Author	Sagehashi, A. Kusaka, K. Orikawa, K. Itoh, J.-I. Momma, A.
Copyright Year	2014
Description	Author affiliation: Product Planning Headquarters, Unipulse Corp., Tokyo, Japan (Momma, A.) \|\| Dept. of Electr., Nagaoka Univ. of Technol., Nagaoka, Japan (Sagehashi, A.; Kusaka, K.; Orikawa, K.; Itoh, J.-I.)
Abstract	This paper investigates differences of parasitic inductances caused by DC bus bar patterns on printed circuit boards(PCB). The DC bus bar pattern on the PCB is limited depending on the layout of main circuits and the control circuits. Two patterns which are a laminated wiring pattern and a plane wiring pattern are compared in experiments and simulations. In this paper, it will be clarified that effects of the DC bus bars on PCBs such as a surge voltage of a switch in terms of the parasitic inductance depending on the circuits on PCBs. As a result, if the same parasitic inductance which is 20 nH, is realized between each wiring pattern at the same length, the plane wiring pattern requires over ten times of the pattern width compared with that of the laminated wiring pattern. Hence, the circuit size can be downsized when the laminated pattern is used. From the experimental results, the maximum surge voltage in the plane wiring pattern is larger than that in the laminated wiring pattern. In this case, the parasitic inductance value of the plane wiring pattern is three times that of the laminated wiring pattern. However, the surge voltage in the laminated pattern is reduced by 7% compared with the plane wiring pattern. As a consequence, the ratio of the surge voltage does not match that of the parasitic inductance. As a result, not only the parasitic inductance of the DC bus bar but also it is necessary to consider other parasitic inductances on PCBs such as parasitic inductances into input capacitors and the path between an upper MOSFET and a lower one and so on.
Starting Page	569
Ending Page	574
File Size	327158
Page Count	6
File Format	PDF
ISBN	9781479920600
DOI	10.1109/EPEPEMC.2014.6980555
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-09-21
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Wiring Inductance Surges Printed circuits Integrated circuit modeling Layout Circuit synthesis laminated printed circuit board parasitic inductance front-loading
Content Type	Text
Resource Type	Article

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