NDLI: Hardware architecture specification and constraint-based WCET computation

Content Provider	IEEE Xplore Digital Library
Author	Herbegue, H. Casse, H. Filali, M. Rochange, C.
Copyright Year	2013
Description	Author affiliation: Inst. de Rech. en Inf. de Toulouse, Univ. de Toulouse, Toulouse, France (Herbegue, H.; Casse, H.; Filali, M.; Rochange, C.)
Abstract	The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the micro-architecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times.
Starting Page	259
Ending Page	268
File Size	259110
Page Count	10
File Format	PDF
ISBN	9781479906581
DOI	10.1109/SIES.2013.6601499
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-06-19
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Registers Hardware Pipelines Syntactics Iron Buffer storage
Content Type	Text
Resource Type	Article

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