NDLI: New Strategies for System-Level Design

Content Provider	IEEE Xplore Digital Library
Author	Gajski, D.D.
Copyright Year	2007
Description	Author affiliation: Univ. of California Irvine, Irvine (Gajski, D.D.)
Abstract	With complexities of Systems-on-Chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what these basic blocks should be and what should be the strategy for creating a system design out of these basic blocks. To make things more difficult, the difference between software and hardware is becoming indistinguishable which, in turn, requires sizable change in the industrial and academic infrastructure. In order to find the solution, we will look first at the system gap between SW and HW designs and derive requirements for the system design flow that includes software as well as hardware. In order to enable new tools for model generation, simulation, synthesis and verification, the design flow has to be well defined with unique abstraction levels, model semantics and model transformations that correspond to design decisions made by designers. We will introduce the concept of model algebra that supports such a design flow and can serve as an enabler for the new approach in globally-collaborative system design and, consequently, global system industry. In order to demonstrate our approach we will use MP3 example and show increased simplicity and huge productivity gains for complex systems. We will explain the benefits and finish with a prediction and a roadmap toward the final goal of increasing productivity by several orders of magnitude while reducing expertise level needed for design of billion-transistor systems to the basic principles of design science only.
Starting Page	15
Ending Page	15
File Size	104398
Page Count	1
File Format	PDF
ISBN	1424411610
DOI	10.1109/DDECS.2007.4295246
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-11
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Content Type	Text

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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